SEFASI Infrastructure Conglomerate: The Exhaustive Stack from Atoms to 0.5 nm Superintelligence

Executive Summary

The most powerful chokepoint on Earth is not oil or nukes, but a machine that weighs 180 tons, contains over 100,000 parts sourced from 5,000 suppliers across 60 countries, and costs over €350 million per unit 1 (https://www.businesstimes.com.sg/companies-markets/telcos-media-tech/chinas-top-chip-bosses-urge-supportive-policies-create-chinas-asml). That machine is ASML's EUV lithography system, and it exists only because of a trinity: Netherlands (ASML integration), Germany (Zeiss mirrors and Trumpf lasers), and Japan/US (photoresist, chemicals, and EDA software).

For SEFASI to move from energy company to infrastructure conglomerate, it must replicate the entire vertical from mine to mind. This report details: every material class required, who owns the design software and what knowledge they hold, the exact parts list for a 0.5 nm super-chip, a sub-10 kW TPU at Nvidia DGX Spark scale (150 mm x 150 mm), a TPU-sized quantum computer, and the full stack needed to rebuild internet, laptops, data centers, robots, and AI from scratch.

1. The Trinity Bottleneck: Why the US-Japan-Netherlands Axis Holds China in Check

1.1 The Machine No Country Can Build Alone

ASML EUV contains over 100,000 components supplied by 5,000 suppliers, with ASML merely serving as the integrator 1 (https://www.businesstimes.com.sg/companies-markets/telcos-media-tech/chinas-top-chip-bosses-urge-supportive-policies-create-chinas-asml). Each system costs nearly $200 million for low-NA and exceeds €350 million for High-NA EXE:5000 2 (https://www.notebookcheck.net/TSMC-secures-350-million-High-NA-EUV-system-for-1-4nm-chip-development.912753.0.html) 3 (https://tech-insider.org/asml-q1-2026-revenue-earnings-guidance-raise-ai-chip/), weighs 180 tons, and requires multiple cargo planes to deliver.

1.2 German Mirrors: The Flattest Surfaces on Earth

Every EUV lithography machine runs on mirrors ground in Oberkochen — mirrors so flat that if expanded to the size of Germany, the highest variation would be 0.1 mm 4 (https://www.navexa.com/the-benchmark/wait-the-ai-industry-depends-on-a-german-family-business-2026-06-25). Carl Zeiss SMT is the sole manufacturer of EUV mirror optics 5 (https://www.sovereignmagazine.com/article/european-semiconductor-companies-chips-act). Without Zeiss optics, ASML could not make its EUV systems. EUV light is absorbed by everything, even air, so there are no lenses at all — only mirrors in vacuum, coated in up to 100 alternating layers of molybdenum and silicon, polished so smooth that scaled to the size of Germany the bump is less than a millimeter.

ASML holds a 24.9% minority stake in Carl Zeiss SMT for roughly €1 billion, described as a virtually merged company 4 (https://www.navexa.com/the-benchmark/wait-the-ai-industry-depends-on-a-german-family-business-2026-06-25).

1.3 German Lasers: Trumpf's Monopoly

Trumpf in Ditzingen builds the CO 2 drive laser amplifier that makes EUV possible. A generator drops tin droplets into vacuum, each droplet smaller than the laser's focus spot. A pulsed CO 2 laser strikes each one 50,000 times per second, ionizing tin into plasma that generates 13.5 nm light 4 (https://www.navexa.com/the-benchmark/wait-the-ai-industry-depends-on-a-german-family-business-2026-06-25). There is no other company on Earth that builds this laser amplifier. Trumpf is 90% owned by the Leibinger family, private, never having to justify to public markets.

Other extreme chokepoints: Trumpf is sole EUV laser source, Zeiss sole optics, ASML sole EUV lithography, IMS Nanofabrication 98% of EUV photomasks, VAT Group 75% of vacuum valves 5 (https://www.sovereignmagazine.com/article/european-semiconductor-companies-chips-act).

1.4 Japanese Photoresist: The Ink

Japan controls over 70% of all photoresist, and roughly 95% of high-end EUV resist 6 (https://privatemarketsnews.substack.com/p/the-japanese-lock-on-photolithography). Four Japanese companies — JSR, Tokyo Ohka Kogyo (TOK), Shin-Etsu Chemical, and Fujifilm — take a combined 72.5% share 7 (https://www.globenewswire.com/en/news-release/2022/01/14/2367042/28124/en/Global-And-China-Photoresist-Industry-Report-2021-2026-Japanese-and-American-Companies-Command-a-Whopping-87-of-the-Highly-Concentrated-Market.html). For EUV, JSR, TOK, and Shin-Etsu account for nearly 85% of EUV resist production volume 8 (https://ranzware.com/japanese-chemical-giant-jsr-expands-to-taiwan-for-euv-photoresist-production-near-tsmc-plant-to-fill-missing-chemical-link-to-scale-euv-materials). Top five players command 87% of highly concentrated market.

Photoresist is the light-sensitive chemical coating that captures circuit pattern onto wafer during exposure — material equivalent of film in camera 9 (https://medium.com/@linda.chan010708/japan-doesnt-make-the-machine-that-prints-2nm-chips-it-makes-the-ink-and-that-might-matter-more-d1fda93f4530). Each new node requires hundreds of iterative test cycles. JSR under new ownership: Japan Investment Corporation completed tender offer in April 2024, delisted June 2024, valued at ¥909 billion ($6.4 B) 8 (https://ranzware.com/japanese-chemical-giant-jsr-expands-to-taiwan-for-euv-photoresist-production-near-tsmc-plant-to-fill-missing-chemical-link-to-scale-euv-materials). Tin-oxide Metal Oxide Resist (MOR) absorbs EUV photons 5 x more efficiently than organic CARs.

1.5 US Controls: Gases and Software

Ukraine supplies nearly 70% of neon gas for lasers used to etch circuit designs 10 (https://koreabizwire.com/ukraine-tensions-feared-to-disrupt-chip-production), and 70% of world's supply of neon is Ukrainian, one company Cryoin supplies 90% of US semiconductor-grade neon 11 (https://www.converge.com/es/resources/news/semiconductor-materials-impacted-by-ukraine-russia-conflict/?wg-choose-original=false). Neon used in DUV excimer-laser gas mixtures. Ukraine also supplies 40% krypton, 30% xenon.

China faces bottlenecks in EDA and basic materials, along with EUV machines 1 (https://www.businesstimes.com.sg/companies-markets/telcos-media-tech/chinas-top-chip-bosses-urge-supportive-policies-create-chinas-asml).

2. Materials: Exhaustive Granular List — What You Actually Need

SEFASI must source or synthesize 300+ distinct material classes. Below is the complete ontology.

2.1 Substrate Foundation


Layer	Material	Purity	Source/Process
Base wafer	Metallurgical Si from quartzite SiO 2 >99.6% + carbon arc 2000 C	9 N to 11 N (99.999999999%)	Wacker, Hemlock, SUMCO, Shin-Etsu
SOI variant	Soitec controls 70-80% SOI wafer production 5 (https://www.sovereignmagazine.com/article/european-semiconductor-companies-chips-act)	-	Smart Cut process
Alternative substrates	Silicon carbide (SiC), Sapphire, GaN-on-SiC for RF/power	-	Wolfspeed, CoorsTek

2.2 Dopants and Channel Materials

Traditional dopants: Boron (p-type), Phosphorus, Arsenic, Antimony (n-type)
Next-gen channel: Hafnium, Cobalt, Ruthenium interconnects, Molybdenum disulfide (MoS 2), Tungsten diselenide (WSe 2), graphene nanoribbons, carbon nanotubes
High-k dielectric: Hafnium oxide HfO 2, zirconium oxide, aluminum oxide
Work function metals: Titanium nitride TiN, TiAl, Mo

2.3 Photoresist Chemistry (Japanese Lock)

CAR (Chemically Amplified Resist): Polyhydroxystyrene derivatives + Photoacid generator (PAG) + quencher + solvent (PGMEA)
MOR (Metal Oxide Resist): Tin-oxide clusters Sn 12 O, Inpria formulation, 5 x smaller building blocks, 10-100 x etch resistance
Suppliers: JSR (25% market), TOK, Shin-Etsu, Fujifilm, Sumitomo Chemical 7 (https://www.globenewswire.com/en/news-release/2022/01/14/2367042/28124/en/Global-And-China-Photoresist-Industry-Report-2021-2026-Japanese-and-American-Companies-Command-a-Whopping-87-of-the-Highly-Concentrated-Market.html)

2.4 Gases — The Invisible Bottleneck

Lithography gases: Neon (70% Ukraine), Argon Fluoride ArF (193 nm), Krypton Fluoride KrF (248 nm), hydrogen, tin vapor
Etch gases: CF 4, CHF 3, C 4 F 6, SF 6, Cl 2, HBr, BCl 3
Deposition gases: Silane SiH 4, dichlorosilane, TEOS, ammonia NH 3, tungsten hexafluoride WF 6, trimethylaluminum
Ultra-pure: 99.9999999% purity required, particle count <1 per cubic meter

2.5 Liquids and Acids

Hydrofluoric acid HF for oxide removal, sulfuric acid H 2 SO 4, hydrogen peroxide H 2 O 2, buffered HF (NH 4 F:HF 7:1), isopropanol, propylene glycol ethers, acetone, phosphoric acid H 3 PO 4 12 (https://github.com/egofree/techtree/blob/HEAD/docs/photolithography/fab-processes.md). RCA clean: NH 4 OH/H 2 O 2/H 2 O and HCl/H 2 O 2/H 2 O.

2.6 Critical Minerals and Metals

Gallium: 98% of global primary production China, 89% productive capacity 13 (https://thoughtleadership.rbc.com/wp-content/uploads/Critical-Minerals-Gallium.pdf), used in GaAs, GaN for power/RF
Germanium, Palladium (1/3 from Russia), Cobalt, Lithium, Tungsten, Tantalum
Rare earths: Neodymium, Dysprosium for motors in robots, Europium for displays
Interconnect metals: Copper (damascene), Cobalt (sub-5 nm), Ruthenium, Molybdenum

2.7 EUV Optics Materials

Mo/Si multilayer mirrors (40-100 layers), Zeiss polishing to atomic precision, vacuum vessels (VDL), tin droplets (99.999% pure Sn), CO 2 laser crystals.

2.8 Packaging Materials

ABF substrate, BT substrate, copper pillars, solder bumps (SnAg), underfill epoxy
HBM memory stacks: Through-silicon vias TSV, microbumps, interposers
Advanced: CoWoS (Chip-on-Wafer-on-Substrate), SoIC, hybrid bonding Cu-Cu

3. Software: Who Designs It, What They Know, Who Owns It

3.1 The EDA Duopoly + Siemens


Company	Founding	Ownership	Market Control
Synopsys	1986 by Aart de Geus, David Gregory, Alberto Sangiovanni-Vincentelli	Public NASDAQ SNPS, 85.5% institutional (BlackRock 8.46%, Vanguard), market cap ~$117 B	45-50% verification VCS, $6 B+ revenue, now owns Ansys
Cadence	1988 merger SDA + ECAD by Richard Newton, Sangiovanni-Vincentelli, James Solomon	Public NASDAQ CDNS, 84.8% institutional, largest EDA under Costello 1988-1997	40-45% Xcelium, 55-60% Palladium emulation
Siemens EDA (Mentor)	Acquired Mentor Graphics 2017 for $4.5 B	Siemens AG	Calibre (physical verification monopoly), Questa

EDA duopoly controls over 80% of $20 B EDA market 14 (https://www.ainvest.com/news/cadence-design-systems-eda-titan-poised-lead-ai-driven-semiconductor-revolution-2506/).

3.2 The Ansys Acquisition — Silicon to Systems

Synopsys completed $35 billion acquisition of simulation leader Ansys 15 (https://www.linkedin.com/pulse/synopsys-completes-35-billion-acquisition-ansys-reshaping-ying-lin-6cwxc), announced Jan 16 2024 16 (https://investors.ansys.com/static-files/090bfd21-8471-4375-b2ab-13e8e994676d). EU approved under conditions Nov 2024 17 (https://www.verdict.co.uk/synopsys-ansys-acquisition-ec-approval/), China approved July 2025 after US lifted EDA ban. Creates leader in silicon to systems design.

3.3 What They Must Know to Design the Software

A senior EDA architect must master:

Computational physics: Electromagnetics (Maxwell for interconnect), quantum transport (NEGF for FinFET/GAA), thermodynamics for thermal simulation (Ansys legacy)
Applied mathematics: Graph algorithms (placement is NP-hard), numerical linear algebra (sparse matrix solvers for 10 B+ nodes), convex optimization, computational geometry
Device physics: TCAD modeling of dopant diffusion, FinFET electrostatics, quantum confinement in 2D materials
Formal methods: Boolean satisfiability SAT solvers for verification, model checking, equivalence checking
Compiler and language design: SystemVerilog, VHDL parsing, synthesis (Design Compiler converts RTL to gates)
Manufacturing knowledge: Design Rule Check DRC 10,000+ rules per node, Optical Proximity Correction OPC, lithography simulation, Design-Technology Co-Optimization DTCO
AI/ML: Reinforcement learning for place-and-route (Google, Synopsys DSO.ai)

This is why China faces bottlenecks in EDA and basic materials 1 (https://www.businesstimes.com.sg/companies-markets/telcos-media-tech/chinas-top-chip-bosses-urge-supportive-policies-create-chinas-asml).

3.4 Software Stack Beyond EDA

Process control: KLA inspection software, Applied Materials APC, Lam Research Equipment Intelligence
Fab execution: MES (Manufacturing Execution Systems), yield management, APC
OPC/RET: Brion (ASML), Mentor Calibre for computational lithography
IP cores: ARM (instruction set), Synopsys/Cadence IP (DDR, PCIe, USB)

4. The 0.5 nm Super Chip: Parts List to Defy Physics

0.5 nm corresponds to 5 angstroms (A 5). IMEC roadmap projects CFET to 5 angstroms in 2032 and 2 angstroms in 2036 18 (https://eu.36kr.com/en/p/3436380564491649).

4.1 Lithography Beyond EUV

High-NA EUV 0.55 NA: TWINSCAN EXE:5000 with 8 nm resolution single exposure, 40% higher imaging contrast than 0.33 NA 2 (https://www.notebookcheck.net/TSMC-secures-350-million-High-NA-EUV-system-for-1-4nm-chip-development.912753.0.html), cost €350 M ( $373 M-$ 400 M) 19 (https://ucl.engins.org/external/angstrom-age-angst-ameliorated-as-asmls-high-na-euv-chipmaking-kit-delivers/view/), throughput 125-175 WPH, half field 26 x 16.5 mm requiring stitching. 10 systems operating at 4 chipmakers as of 2026.
Hyper-NA EUV 0.75 NA: Anamorphic optics, 12-inch reticles, price projected $720 M by 2030
Alternative: Free-electron laser (xLight startup funded $150 M by US Commerce to replace Trumpf CO 2), EUV pellicles (EUV transparent membranes), MOR resist

4.2 Transistor Architecture Evolution


Node Target	Architecture	Key Feature	Source
3-5 nm	FinFET/GAA Nanosheet	Gate on 3 or 4 sides	Current
~2 nm	Forksheet FET	Shared dielectric wall, 17 nm n-p pitch	imec
sub-2 nm	CFET (Complementary FET)	PMOS stacked atop NMOS, halves cell footprint	20 (https://github.com/normansrule/transistor-odyssey/blob/HEAD/docs/08-gaa-and-angstrom-era.md)
0.7 nm	Staggered CFET	First demo IBM 0.7 nm	IBM
0.5 nm (A 5)	CFET + 2D TMDs	Vertically integrated, MoS 2 channels	18 (https://eu.36kr.com/en/p/3436380564491649)
0.2 nm	2D materials only	Monolayer channels, no body variation	IRDS

CFET integrates n-type and p-type devices compactly, stacking pFET directly on nFET 21 (https://printingpressai.com/article/robotics/chip-industry-technical-paper-roundup-sept-29). Reduction in area enables density.

4.3 Materials for 0.5 nm

Channel: Transition metal dichalcogenides TMDs MoS 2, WSe 2, WS 2 monolayer (0.65 nm thick, no dangling bonds)
Gate: CFET with buried power rails, non-metallic gate cut, intermediate dielectric insulation for work function separation (Lam SA-CFET)
Interconnect: Backside Power Delivery Network (BSPDN) — power distribution in back of wafer, signals front side, enables lower power and increased density 22 (https://blogs.sw.siemens.com/calibre/2026/09/30/solving-the-extraction-challenges-of-cfet-and-backside-power/). Branded PowerVia by Intel, Super Power Rail by TSMC A 16 22 (https://blogs.sw.siemens.com/calibre/2026/09/30/solving-the-extraction-challenges-of-cfet-and-backside-power/) 23 (https://www.trendforce.com/news/2024/07/03/news-tsmcs-backside-power-delivery-reportedly-set-for-2026-benefiting-the-supply-chain/)
Metrology: Atomic precision, 30 nm superconducting wires demonstrated by imec for Josephson junctions, 3.8 M junctions/cm 2

4.4 Equipment List for 0.5 nm Fab

High-NA EUV scanner, e-beam direct write for R&D, atomic layer deposition ALD (precursors from JSR Yamanaka Hutech), atomic layer etch ALE, cryogenic etch, EUV actinic inspection, e-beam inspection, 3D X-ray

5. Sub-10 kW TPU at Nvidia Spark Scale: From 20 W Brain to 10 kW AI

5.1 Baseline: Nvidia DGX Spark (Project DIGITS)

GB 10 Grace Blackwell Superchip co-designed with MediaTek 24 (https://www.thefreelibrary.com/Nvidia%E2%80%99s+DGX+Spark+desktop+supercomputer+is+on+sale+now%2c+but+hard+to…-a0860691268): 20-core Arm (10 x Cortex-X 925 + 10 x Cortex-A 725), Blackwell GPU with 5 th-gen Tensor Cores FP 4, 1 petaflop FP 4 sparse 25 (https://hkbusinesswire.com/midea-showcases-breakthrough-cooling-technologies-for-high-density-ai-data-centers-at-data-center-world-asia-2026/)
128 GB LPDDR 5 x unified memory 273 GB/s, 8533 MT/s, 256-bit bus
240 W power supply, GB 10 TDP 140 W, 100 W for other components 26 (https://www.tomshardware.com/pc-components/gpus/nvidia-dgx-spark-review/2)
Form 150 mm L x 150 mm W x 50.5 mm H, 1.2 kg 27 (https://www.scan.co.uk/products/nvidia-dgx-spark-personal-ai-supercomputer-gb10-blackwell-superchip-4tb-ssd-128gb-lpddr5x-connectx7), ConnectX-7 Smart NIC 200 Gb/s, NVLink-C 2 C 5 x PCIe Gen5

Predecessor DGX-1 required 3,200 W. Spark is 240 W delivering same class.

5.2 The Brain Efficiency Gap

Brain manages 50 million billion operations per watt (1 e 18 ops/s /20 W =5 e 16 ops/W). H 100 about 100 billion operations per watt (67 e 12 ops/s /700 W =1 e 11 ops/W) 28 (https://medium.com/@samuel.sperling/could-silicon-ever-match-the-brains-energy-budget-8c67ebe321ec). Gap ~500,000 x.

Human brain vs AI: brain runs on 12-20 W, detailed emulation could require 2.7 gigawatts 29 (https://currato.com/human-brain-vs-ai-your-brain-runs-on-less-power-than-a-light-bulb-outperforming-supercomputers-yet-ai-needs-entire-data-centres-to-compete/). Brain achieves efficiency through sparse neural firing, analogue signaling, massive parallelism.

Brain uses ~20 W constant budget, while AI data centers dissipate megawatts to gigawatts 30 (https://www.eetimes.com/the-human-brain-versus-ai-similar-results-very-different-machines/).

5.3 Parts Needed for Sub-10 kW TPU at Spark Size

To go from 240 W to sub-10 kW for data-center-class performance (10 kW is 41 x Spark but targeting cluster-level in box), or to sub-100 W for same perf:

Advanced packaging: CoWoS-L, SoIC-X 3D stacking, hybrid bonding Cu-Cu direct, 10+ HBM 4 stacks (each 1.2 TB/s), wafer-scale interposer
Memory: 256 GB-1 TB LPDDR 6 / HBM 4 unified, 1 TB/s+ bandwidth, in-memory computing (analog crossbars), processing-in-memory PIM
Interconnect: Silicon photonics optical I/O, co-packaged optics CPO, NVLink-C 2 C successor, 1.6 T Ethernet
Power: GaN power delivery, integrated voltage regulators FIVR, backside power delivery BSPDN reduces IR drop 10 x
Cooling: Direct liquid cooling cold plates, magnetic bearing CDU, power-cooling hyperconverged architecture 31 (https://hkbusinesswire.com/midea-showcases-breakthrough-cooling-technologies-for-high-density-ai-data-centers-at-data-center-world-asia-2026/)
Compute paradigm shift (to reach brain 20 W): Must redesign AI information itself:

Spiking Neural Networks SNNs: Only fire when data changes, 100-1000 x energy efficiency over conventional 32 (https://www.mdpi.com/2079-9292/15/18/4309), 2-3 x better for temporal tasks and 1000 x more efficient neural communication 33 (https://www.programming-helper.com/tech/neuromorphic-computing-2026-brain-inspired-chips-revolutionizing-ai-energy-efficiency)
Neuromorphic: Intel Loihi 2, IBM TrueNorth, event-driven, memory+compute co-located, no von Neumann bottleneck 34 (https://www.webpronews.com/brain-mimicking-chips-cut-ais-energy-thirst/)
State-space models (Mamba), sparsity, mixture-of-experts MoE, quantization FP 4/INT 4, analog computing: No data converters needed due to analog nature

If we obey physics, 20 W brain proves sub-10 kW superchip is not only possible but still 500 x inefficient vs biology. Path is not just better transistors but abandoning digital dense matrix multiply for sparse event-driven compute.

6. Quantum Computer the Size of a TPU

6.1 Current Quantum Reality

Google Sycamore 53 qubits: 10 mm chip, aluminum and indium between two silicon wafers, aluminum-niobium loops, requires dilution refrigerator <20 mK, 277 DACs. IBM Condor 1121 qubits needs Goldeneye fridge 6-foot wide and 12-foot high.

6.2 Materials and Parts for TPU-Sized Quantum


Component	Material/Part	Why Needed
Qubit	Josephson junction: Al/AlOx/Al or NbN/AlN/NbN, NbTiN	Superconducting at millikelvin, zero resistance 35 (https://markets.financialcontent.com/custercountychief/article/tokenring-2025-12-1-quantums-cryogenic-crucible-semiconductor-innovations-pave-the-way-for-scalable-computing)
Substrate	High-resistivity silicon, sapphire, Si with isotopically pure Si-28, diamond NV centers	Reduce decoherence
Cryogenics	Dilution refrigerator (He-3/He-4 mix), pulse tube cryocooler, cryogenic vacuum	Achieve 10-15 mK regime, major size bottleneck
Control electronics	Cryo-CMOS at 4 K, RFSoC, 14-bit DACs 1 GHz, attenuators, filters	Must move from room-temp racks to cryogenic chips
Interconnect	Niobium superconducting wires 30 nm linewidth, 3.8 M junctions/cm 2 (imec) 36 (https://jweasytech.com/2026/09/15/imec-advances-scalable-superconducting-technology-with-world-first-nbtin-circuits-and-30nm-interconnects/)	Scale to millions of qubits
Packaging	Hermetic enclosure, magnetic shielding, IR shielding	Protect quantum states
Alternative paths	Trapped ion (Ytterbium-171, laser-cooled), photonic (silicon photonics + single photon detectors), silicon spin qubits (Quantum dots)	Room-temp control possible for photonic/trapped ion, larger but no dilution fridge

To shrink to TPU size (150 mm), need:

Replace large dilution fridge with on-chip cryocooling (research: all-nitride qubits NbN 16 K transition 37 (https://phys.org/news/2021-09-all-nitride-superconducting-qubit-silicon-substrate.html) higher temp than Al)
Integrate control electronics into cryo-CMOS SoC (like Nvidia GB 10 concept but cryogenic)
Photonic interconnect between modules
Error correction overhead: 1000 physical per logical qubit — need materials improvement to reduce to 10:1

This is 10-year horizon. Near-term TPU-sized quantum will be photonic (PsiQuantum, Xanadu) operating at 4 K not 10 mK.

7. Full Vertical Stack: Building Everything From Scratch

If SEFASI must create own internet, laptops, data centers, robots, and AI:

7.1 Mining to Refining

Silicon: Quartz mine → carbothermic reduction → Siemens process trichlorosilane → Czochralski crystal pulling → wafer slicing → polishing
Copper: Mine (Zambia has copper) → flotation → smelting → electrorefining 99.99% for PCBs
Battery metals: Lithium brine/hard rock, cobalt (DRC 75%), refining China 65% Li, 89% Co, 99% natural graphite 13 (https://thoughtleadership.rbc.com/wp-content/uploads/Critical-Minerals-Gallium.pdf)
Gallium/Germanium: Byproduct bauxite/zinc, China 98% primary gallium 13 (https://thoughtleadership.rbc.com/wp-content/uploads/Critical-Minerals-Gallium.pdf)

7.2 Chemical Industry

Must build: HF plant, sulfuric acid, hydrogen peroxide, PGMEA solvent, high-purity gas purification, photoresist synthesis (JSR-level chemistry), CVD precursors (Yamanaka Hutech acquired by JSR).

7.3 Wafer Fab

Cleanroom ISO 1-3, air filtration, vibration isolation, EUV scanners, etch (Lam, TEL), deposition (Applied Materials), CMP, ion implant, metrology (KLA)
PDK development: 1000+ design rules

7.4 PCB and Assembly

Copper clad laminate, ABF film, drilling, plating, SMT lines, OSAT (ASE, Amkor) for packaging

7.5 Internet Infrastructure

Physical: Fiber optic glass preforms (Corning), drawing towers, undersea cable ships, repeaters with Erbium-doped fiber amplifiers pumped by 980 nm lasers, steel armor for 50-year lifespan 38 (https://www.linkedin.com/posts/kenkuang_massive-fiber-optic-cables-are-carefully-activity-7449818772497924097-fYF7)
Active: Routers (Cisco, Juniper), optical transceivers, IP/MPLS stack, DNS (BIND), TCP/IP, BGP, IXPs
Backbone: 750,000 miles fiber carrying 99% intercontinental traffic 39 (https://www.techspot.com/news/112014-cables-powering-internet-under-ocean-under-threat.html), Google/Meta/Microsoft private cables $15 B U.S.-India Connection 40 (https://abit.ee/en/hard/wi-fi-routers-modems/google-undersea-cable-us-india-connection-fiber-optic-internet-infrastructure-vishakhapatnam-google-en)
To own internet: need autonomous system number ASN, submarine cable landing rights, peering agreements, satellite backup (Starlink alternative)

7.6 Laptops

Display (LCD/OLED from LG/Samsung, driver IC), battery (Li-ion cells, BMS), chassis (aluminum CNC), keyboard, trackpad, motherboard, CPU/GPU (your 0.5 nm chip), WiFi 7, SSD
OS: Linux kernel + drivers

7.7 Data Centers

Power: Transformers, UPS, diesel gensets, Li-ion BESS, PDU, busbars, GaN PSUs
Cooling: Chillers 5 GW contracts 41 (https://biz.chosun.com/en/en-it/2026/10/05/W4EGPF2OZZCQZFQZVM3UM4ZYLU/), CDUs, direct liquid cold plates, immersion tanks, magnetic bearing cooling 31 (https://hkbusinesswire.com/midea-showcases-breakthrough-cooling-technologies-for-high-density-ai-data-centers-at-data-center-world-asia-2026/)
Servers: Racks, NVLink switches, InfiniBand, storage (NVMe), orchestration (Kubernetes)
Building: Concrete, steel, fire suppression, security

7.8 Robots

Actuators: Harmonic drives (Japan Harmonic Drive monopoly), brushless motors, encoders
Sensors: LIDAR (Velodyne), force-torque, IMU, depth cameras
Compute: Your TPU, ROS, real-time OS
Materials: Aluminum alloys, carbon fiber, rare-earth magnets (NdFeB)

7.9 AI Stack

Training cluster (10 k+ TPUs), framework (PyTorch, JAX), compiler (XLA, Triton), model architecture (transformer → SSM → SNN), quantization pipeline, inference server (vLLM), alignment

8. SEFASI as Infrastructure Conglomerate: Strategic Roadmap

SEFASI's origin in sustainable energy is the wedge, not the identity. Energy is prerequisite for compute. Strategy:

Phase 1: Energy-to-Compute (0-2 years)

Deploy solar + storage in Zambia (copper belt) to power 20 MW pilot data center. Zambia's copper provides PCB raw material.
Build chemical purification lab for HF, photoresist R&D with JSR/TOK partnerships (Taiwan Yunlin model 8 (https://ranzware.com/japanese-chemical-giant-jsr-expands-to-taiwan-for-euv-photoresist-production-near-tsmc-plant-to-fill-missing-chemical-link-to-scale-euv-materials))
EDA talent: Recruit 10 engineers mastering graph algorithms, device physics, SAT solvers

Phase 2: Substrate and Packaging (2-4 years)

Joint venture for quartz → metallurgical Si → wafer reclaim, leveraging African quartz reserves
Advanced packaging facility: CoWoS-like interposer, hybrid bonding, HBM integration — lower capex than front-end fab, $200 M vs $20 B
Build Spark-class TPU using chiplets + LPDDR 5 X + GaN power, targeting 240 W first, then sub-100 W via sparsity

Phase 3: Front-End Sovereignty (4-7 years)

Acquire DUV lithography (ASML NXT), develop MOR with tin-oxide chemistry
CFET R&D with imec membership, backside power delivery pilot
Secure neon/krypton supply via air separation from steel plants (Ukraine model) — Zambia steel industry opportunity

Phase 4: 0.5 nm and Quantum (7-12 years)

High-NA EUV access via consortium (Intel model: first to install EXE:5000)
2D materials: CVD MoS 2 growth, transfer techniques
Quantum: Start with photonic, not superconducting, to avoid dilution fridge. Partner with Si photonics foundry.
Brain-inspired: Fund neuromorphic SNN research targeting 1,000 x efficiency 33 (https://www.programming-helper.com/tech/neuromorphic-computing-2026-brain-inspired-chips-revolutionizing-ai-energy-efficiency)

Moat: Unlike Trumpf and Zeiss private foundation structures 4 (https://www.navexa.com/the-benchmark/wait-the-ai-industry-depends-on-a-german-family-business-2026-06-25), SEFASI as foundation-owned conglomerate can sustain 30-year R&D that public markets would kill — exactly why Nikon/Canon concluded atomic-precision optics was impossible.